linting
using vscode extension Verilog-HDL/SystemVerilog/Bluespec SystemVerilog
.
using iverilog
go to extension settings and set verilog > linting : linter = iverilog
then the linting function should work for verilog files.
Notice:
- the dir to verilog file should not contain chinese characters and spaces.
- if you imported module from other file without
include
command, iverilog willl report an error. As it is always the case when using vivado, add-i
to extention settingVerilog › Linting › Iverilog: Arguments
to ignore this error.